The present invention relates to an integrated circuit with a plurality of active strip-shaped regions arranged in parallel next to one another and a contact level with a respective plurality of contacts arranged regularly in the longitudinal direction of the individual strip-shaped regions.
Although in principle it can be applied to any desired integrated circuit, the present invention and the problems on which it is based are explained with respect to integrated OCD (Off Chip Driver) circuits in silicon technology.
FIG. 3 is a schematic lateral representation of a known integrated circuit in silicon technology.
In FIG. 3, reference numeral 1 designates a semiconductor substrate, for example a silicon semiconductor substrate. Integrated into the semiconductor substrate 1 are source/drain regions 2, 4 with a channel region 3 lying in between. When considered in plan view (cf. FIG. 4), the source/drain regions 2, 4 are elongate strips, which have on the substrate surface a substantially rectangular cross section, the strips being arranged parallel to one another.
Also with reference to FIG. 3, provided above the substrate surface is a first contact level K1, which has for each of the source/drain regions 2, 4 a plurality of contacts 6, 7 arranged regularly in the longitudinal direction. In the present example, the contacts 6, 7 lie substantially in the center of the strip-shaped source/drain regions 2, 4 and are spaced equidistantly apart. The contacts 6, 7 are embedded in an insulating layer 5, which consists for example of TEOS oxide.
Provided above the first contact level K1 is a first metallization level M0, which electrically connects the contacts 6, 7 to metal areas 8a, 8b, for example of tungsten, which are electrically isolated from one another. Provided above the metal level M0 is a second contact level K2, which in the present case respectively provides two contacts 9, 10 and 11, 12 above the corresponding contact of the first contact level K1, that is to say above the contacts 6, 7. A further insulating layer between the contacts 9, 10, 11, 12 is not shown for reasons of overall clarity.
Above the contact level K2 there lies a further metallization level M1, which brings together the contacts 9, 10 by means of the metal area 13a and the contacts 11, 12 by means of the metal area 13b. 
FIG. 4 is a schematic plan-view representation of the known integrated circuit in silicon technology.
According to the representation of FIG. 4, in the present example 5 source/drain regions S1, D1, S2, D2, S3 are provided, the regions S1 and D1 corresponding to the regions 2 and 4 of FIG. 3. The length of the source/drain regions S1, D1, S2, D2, S3 will be designated hereafter by L. Provided between the source/drain regions S1, D1, S2, D2, S3 there is respectively a channel region with a gate terminal G1-G4 lying over it. The squares filled with a cross in FIG. 4 designate the upper view of the contacts of the first contact level K1 which, as already mentioned, lie substantially in the center of the widthwise extent of the respective source/drain regions S1, D1, S2, D2, S3.
The open squares in FIG. 4 designate the contacts of the second contact level K2, which are connected via the first metallization level M0 to the corresponding contacts of the first contact level K1. Consequently, in the present case, a specific contact of the first contact level K1 is respectively connected to two contacts lying above it of the second contact level K2, to be precise, according to the representation of FIG. 4, in each case to the nearest neighbor lying above it to the left and right. In FIG. 3, allowance is made for the fact that the contacts of the two contact levels K1, K2 are offset in relation to each other in the longitudinal direction, in that the contacts 6, 7 have a different hatching than the contacts 9, 10, 11 and 12.
The problems occurring in the case of the integrated circuit explained with reference to FIGS. 3 and 4 lie in the design rules for the configuration of the contacts and the configuration of the metallizations. In particular, problems arise in the case of the arrangement shown if the width of the channel region 3 or the gates G1-G4 lying over it is reduced. As from a certain width, the nearest neighboring contacts of two neighboring source/drain regions of the second contact level K2 then collide.
This problem could be easily solved by in each case only every second strip-shaped source/drain region S1, D1, S2, D2, S3 having double contacts in the second contact level K2, i.e. if the source/drain regions alternately contained two contacts and then one contact in the second contact level K2. However, this is disadvantageous inasmuch as each source/drain region is to be uniformly connected to the power supply, i.e. each source/drain region has a substantially equal output and input resistance. A symmetry of the source/drain regions is also desirable with regard to electrical bonding, in order that a substantially homogeneous current density distribution is obtained over the surface area of the entire source/drain regions.
It is therefore an object of the present invention to provide a corresponding integrated circuit, it being possible to provide a plurality of contacts distributed over the width in the second contact level without problems occurring in respect of the narrowing of the channel regions.
This object is achieved according to the invention by the integrated circuit disclosed herein.
The idea on which the present invention is based is that the contacts are arranged in the widthwise direction of the individual strip-shaped regions in such a way that the widthwise extent of corresponding contacts of neighboring regions varies.
One advantage which the circuit according to the invention has over the known approach to a solution is that, in spite of a reduction in the dimensions, a symmetry of the contacts and an equal number of them can be retained for each active region.
Advantageous developments and improvements of the subject matter of the invention can be found in the subclaims.
According to a preferred development, the contacts of the strip-shaped regions have a first widthwise extent over a first length and a second widthwise extent over a second length.
According to a further preferred development, the widthwise extent of corresponding contacts of a first neighboring strip and a second neighboring strip amounts to two contacts over the first length and one contact over the second length in the case of the first strip and amounts to two contacts over the second length and one contact over the first length in the case of the second strip.
According to a further preferred development, the contacts with the widthwise extent of one contact are arranged substantially in the middle of the width of the respective region.
According to a further preferred development, the strip-shaped regions are source/drain regions of field-effect transistors, which are introduced into a semiconductor substrate with respective channel regions lying in between.
According to a further preferred development, a further contact level, which lies under the contact level and has a respective plurality of contacts arranged regularly in the longitudinal direction of the individual strip-shaped regions, is provided, the contacts of the further contact level having a widthwise extent of one contact.
According to a further preferred development, the two contact levels are interconnected via a metal level lying in between.
According to a further preferred development, the number of contacts of each of the strip-shaped regions is equal.
According to a further preferred development, certain contacts of the contact level of a strip-shaped region lie above a neighboring strip-shaped region.
According to a further preferred development, the strip-shaped regions are substantially rectangular.